Event-Driven Analog and AMS Verification

A number of good papers were recently posted on the BMAS conference site that further developed the ideas of event-driven analog for AMS Verification and I thought I would mention them here.


“A Modeling Methodology For Verifying Functionality Of A Wireless Chip” by Jesse Chen: This paper describes a PLI modeling approach similar to what I and others had advocated.  I think that its strongest contribution is the section describing how to create Baseband Equivalent Models for a PLL and a Filter using Event Driven Analog models.  In it, Jesse shows how to model I, Q, Bandwidth, Carrier-Frequency and Amplitude as separate baseband components.

With regard to software, this paper describes a PLI modeling capability called a “hyperwire.”  This concept seems similar to the idea of “channels” described in my own event-driven analog work [http://tsheffler.com/software/slam/ana].

Another good read is “Event Driven Analog Modeling For The Verification Of PLL Frequency Synthesizers.”  This paper describes the modeling of a PLL using Verilog AMS and a “wreal” approach.

The major EDA tool vendors continue to fail to offer commercial tools to enable high-speed event-driven analog modeling.  The need is there now, but perhaps not a large enough market to justify tool development.  These papers do a good job of describing modeling approaches that effectively use event-driven analog constructs.

3 thoughts on “Event-Driven Analog and AMS Verification”

  1. Since I wrote this post there has been some more recent activity on the front of event-driven analog modeling. The real-number modeling group “SV-DC” has formed as a subcommittee of the SystemVerilog working group. The introduction to their charter reads as follows:

    Excerpt from: https://docs.google.com/document/edit?id=1AYYpLf0c1-528BuA_A4srQLB6MEdw0_Q4NNHkOl2fdE&hl=en&authkey=CKGsmKYJ

    SV-DC intends to provide capabilities in SystemVerilog to support efficient modeling of analog/mixed-signal circuit components. These models are to be simulated by the event-driven simulation engine and should, therefore, exhibit simulation performance comparable to digital models and be suitable for system level simulation. The new modeling capabilities will be achieved by natural extensions to the existing SystemVerilog language; no analog solvers or netlist manipulations will be required.

    A short overview of the effort can be read here:

    Will Evolving Language Standards Address Mixed-Signal Verification Problems?

  2. Here’s an excerpt from a great article in “Tech Design Forum” by Chris Edwards.

    No-one in their right mind expects to be welcomed with open arms when they tell analog designers they should be using digital techniques to design their circuits, as Tom Beckley, senior vice president of R&D for custom ICs at Cadence Design Systems, remarked in his keynote at CDNLive EMEA in May. And Professor Mark Horowitz of Stanford University was under no illusions about that when presenting the IEEE CEDA talk at the Design Automation Conference (DAC) last week.

    What’s cool about Horowitz’s talk is the conjecture that “all systems have linear intent.”


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