Verilog and Python together Again: Cocotb

It has been a few years since there has been a new project embedding the Python interpreter into Verilog. There is a new one on the block, called “Cocotb” built with a definite focus on writing testbenches and running regressions. It is written in a modern dialect of Python and hosted on Git. It is well-documented. I’m impressed with what I’ve seen.

This article gives a little bit of a history of Python and Verilog and describes how Cocotb fits in.

A Brief History

ScriptEDA (2001) [,] was primarily an example of using SWIG to link a Python interpreter into a Verilog simulator using PLI/VPI.  ScriptEDA handled TCK, Perl and Python in roughly the same way.

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