To date, the examples I have shown using switch-level analog (SLA) model systems with sources. switches and resistors. The SLA package also provides op-amps and dependent sources. These can be used to model systems that exhibit some interesting feedback behavior.
Why use event-driven analog models? The need stems from the type of response chekers that are easy to write. A successful test of a system that yields useful information requires three things:
- a correctness criterion (a response checker, when automated)
- an appropriate model (the simulation model)
- a procedure (how do I use the two above things?)
For some types of circuits, it is possible to write a response checker (correctness criterion) that checks a particular value at a particular time. In clocked digital systems, a logic value may remain constant for an entire cycle, which is why cycle-based checkers are sufficient. When an analog correctness criterion is specified to the cycle level, it is best that the models also elide sub-cycle non-idealities in the interest of simplicity and runtimes. Hence, the applicability of event-driven analog models.
Back to the example
This example is illustrative of a feedback techinique used to regulate a supply voltage. A reference voltage is compared to a voltage drop produced over a resistor by a voltage-controlled current-source. In practice, one might see such structures replicated across a chip, providing locally generated bias voltages.
This particular subcircuit has a sample-and-hold device that is triggered by the digital logic periodically to re-calibrate the circuit. When it is not being calibrated it is not tracking voltage changes. (The selective use of calibration might be desired so that the subcircuit is not tracking changes when an important operation is taking place.) When it is tracking, the circuit converges on the new value.
The verilog code for the sample-and hold circuit is shown below.
/* * Sample/hold * Pass the new value through when on. * Hold the old value while off. */ module sample_hold(input sh, inout wire sample, inout wire hold); real sampleval; real holdval; real holdcurrent; /* Instantiate components */ initial begin $slam_sla_vprobe("p1", sample, sampleval); holdval = 0.0; $slam_sla_vsrc("v1", hold, top.GND, holdval, holdcurrent); end /* Behavior */ always @(sampleval, sh) begin if (sh == 1) begin holdval <= #10 sampleval; end end endmodule // sample_hold
Our sample and hold model represents a circuit with a non-zero delay value. We used a delay of #10. The example stimulus was set up to calibrate after a reset occurs and again after a period of time. A waveform dump appears below.
What we observe is that the event-driven model of this circuit converges to a steady state value after a few cycles. After convergence is reached, no more events are triggered and all simulation components related to the circuit stop being evaluated. Thus, each evaulation of the feedback circuit is fairly cheap (in simulation terms) and the correctness criterion is simple (the reached voltage is the same as the reference).
What have we checked here?