Event-Driven Analog and AMS Verification

A number of good papers were recently posted on the BMAS conference site that further developed the ideas of event-driven analog for AMS Verification and I thought I would mention them here.


“A Modeling Methodology For Verifying Functionality Of A Wireless Chip” by Jesse Chen: This paper describes a PLI modeling approach similar to what I and others had advocated.  I think that its strongest contribution is the section describing how to create Baseband Equivalent Models for a PLL and a Filter using Event Driven Analog models.  In it, Jesse shows how to model I, Q, Bandwidth, Carrier-Frequency and Amplitude as separate baseband components.

With regard to software, this paper describes a PLI modeling capability called a “hyperwire.”  This concept seems similar to the idea of “channels” described in my own event-driven analog work [http://tsheffler.com/software/slam/ana].

Another good read is “Event Driven Analog Modeling For The Verification Of PLL Frequency Synthesizers.”  This paper describes the modeling of a PLL using Verilog AMS and a “wreal” approach.

The major EDA tool vendors continue to fail to offer commercial tools to enable high-speed event-driven analog modeling.  The need is there now, but perhaps not a large enough market to justify tool development.  These papers do a good job of describing modeling approaches that effectively use event-driven analog constructs.