Event-Driven Analog Modeling for Verilog
The packages here were born out of my experiences with a modeling challenge.
- I had a design that was mostly digital, but which contained a few analog circuits whose coarse behavior was mostly defined at the time steps of the digital portion.
- I wanted to model the analog effect of the digital control so that I could check the analog value as part of the verification process.
- I wanted the effort to incrementally add models for the analog blocks to be small and localized, since they were a relatively small part of the entire design.
- I wanted the simulation overhead to be minimal.
Two PLI tools were born out of these desires. The first, the "analog values" package was inspired by work done by Chris Jones and Jeff McNeal at Synopsys and gives one the ability to model real values flowing through Verilog wires. With this capability, it is possible to model signal-flow graphs in Verilog, where the signals are real values.
The second, the "switch-level analog" package gives one the ability to model electrical networks. Here, both the voltage on nodes and the currents on branches are of interest. The tool computes KCL at each Verilog event and reports the new steady-state value through real-valued registers.